Practical Challenges for Industrial Formal Verification Tools

Formal verification of digital systems, from ASICs to HW/SW codesign-a pragmatic approach p. 3 The industrial success of verification tools based on Stalmarck's method p. 7 Formal verification-application and case studies p. 11 Automatic abstraction techniques for propositional mu-calculus model checking p. 12 A compositional rule for hardware design refinement p. 24 Module checking revisited p. 36 Using compositional preorders in the verification of sliding window protocol p. 48 An efficient decision procedure for the theory of fixed-sized bit-vectors p. 60 Construction of abstract state graphs with PVS p. 72 Verification of a chemical process leak test procedure p. 84 Automatic datapath extraction for efficient usage of HDD p. 95 An n log n algorithm for online BDD refinement p. 107 Weak bisimulation for fully probabilistic processes p. 119 Towards a mechanization of cryptographic protocol verification p. 131 Efficient model checking using tabled resolution p. 143 Containment of regular languages in non-regular timing diagram languages is decidable p. 155 An improved reachability analysis method for strongly linear hybrid systems p. 167 Some progress in the symbolic verification of timed automata p. 179 STARI: A case study in compositional and hierarchical timing verification p. 191 A provably correct embedded verifier for the certification of safety critical software p. 202 Model checking in a microprocessor design project p. 214 Some thoughts on statecharts, 13 years later p. 226 On-the-fly model checking under fairness that exploits symmetry p. 232 Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation p. 244 Parallelizing the Murphi verifier p. 256 A new heuristic for bad cycle detection using BDDs p. 268 Efficient detection of vacuity in ACTL formulas p. 279 Model checking and transitive-closure logic p. 291 Boolean and 2-adic numbers based techniques for verifying synchronous designs p. 303 Programs with quasi-stable channels are effectively recognizable p. 304 Combining constraint solving and symbolic model checking for a class of systems with non-linear constraints p. 316 Relaxed visibility enhances partial order reduction p. 328 Partial-order reduction in symbolic state space exploration p. 340 Deadlock checking using net unfoldings p. 352 Trace table based approach for pipelined microprocessor verification p. 364 On combining formal and informal verification p. 376 Efficient modeling of memory arrays in symbolic simulation p. 388